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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC14489/D
Multi-Character LED Display/Lamp Driver
CMOS
The MC14489 is a flexible light-emitting-diode driver which directly interfaces to individual lamps, 7-segment displays, or various combinations of both. LEDs wired with common cathodes are driven in a multiplexed-by-5 fashion. Communication with an MCU/MPU is established through a synchronous serial port. The MC14489 features data retention plus decode and scan circuitry, thus relieving processor overhead. A single, current-setting resistor is the only ancillary component required. A single device can drive any one of the following: a 5-digit display plus decimals, a 4-1/2-digit display plus decimals and sign, or 25 lamps. A special technique allows driving 5 1/2 digits; see Figure 16. A configuration register allows the drive capability to be partitioned off to suit many additional applications. The on-chip decoder outputs 7-segment-format numerals 0 to 9, hexadecimal characters A to F, plus 15 letters and symbols. The MC14489 is compatible with the Motorola SPI and National MICROWIRETM serial data ports. The chip's patented BitGrabberTM registers augment the serial interface by allowing random access without steering or address bits. A 24-bit transfer updates the display register. Changing the configuration register requires an 8-bit transfer. * * * * * * * * * * Operating Voltage Range of Drive Circuitry: 4.5 to 6 V Operating Junction Temperature Range: - 40 to 130C Current Sources Controlled by Single Resistor Provide Anode Drive Low-Resistance FET Switches Provide Direct Common Cathode Interface Low-Power Mode (Extinguishes the LEDs) and Brightness Controlled via Serial Port Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI in Low-Power Mode Power-On Reset (POR) Blanks the Display on Power-Up, Independent of Supply Ramp Up Time May Be Used with Double-Heterojunction LEDs for Optimum Efficiency Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.) See Application Note AN431, Temperature Measurement and Display Using the MC68HC05B4 and the MC14489 and Engineering Bulletin EB153, Driving a Seven-Segment Display with the NEURON(R) CHIP
20 1
MC14489
P SUFFIX PLASTIC DIP CASE 738
20 1
DW SUFFIX SOG PACKAGE CASE 751D
ORDERING INFORMATION
MC14489P MC14489DW Plastic DIP SOG Package
PIN ASSIGNMENT
f e VDD d c b a Rx BANK 1 ENABLE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 g h DATA OUT BANK 5 BANK 4 BANK 3 VSS BANK 2 DATA IN CLOCK
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3 10/95
(c) Motorola, Inc. 1995 MOTOROLA
MC14489 1
BLOCK DIAGRAM
12 D C 10 4 24-1/2-STAGE SHIFT REGISTER 4 4 4 4 4 PIN 3 = VDD PIN 14 = VSS 18
DATA IN CLOCK
11
DATA OUT
ENABLE
BitGrabber CONFIGURATION REGISTER 8 BITS
BitGrabber DISPLAY REGISTER 24 BITS 4 4 4 4 4 4
POR
OSCILLATOR AND CONTROL LOGIC 5
5
NIBBLE MUX AND DECODER ROM 7 a TO g h DIM/BRIGHT 8
BLANK
BANK SWITCHES (FETs) 9 13 15 16 17 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 7 a
ANODE DRIVERS (CURRENT SOURCES) 6 b c 5 4 2 1 20 19 de f gh
Rx
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin Parameter DC Supply Voltage DC Input Voltage Value Unit V V V - 0.5 to + 6.0 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 15 Vout Iin DC Output Voltage DC Input Current -- per Pin (Includes Pin 8) mA mA Iout DC Output Current -- Pins 1, 2, 4 - 7, 19, 20 Sourcing Sinking - 40 10 320 Pins 9, 13, 15, 16, 17 Sinking Pin 18 15 IDD, ISS TJ DC Supply Current, VDD and VSS Pins Chip Junction Temperature 350 mA C - 40 to + 130 RJA Device Thermal Resistance, Junction-to-Ambient (see Thermal Considerations section) Plastic DIP SOG Package Storage Temperature C/W 90 100 Tstg TL - 65 to + 150 260 C C Lead Temperature, 1 mm from Case for 10 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14489 2
MOTOROLA
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TJ = - 40 to 130C* unless otherwise indicated)
Symbol VDD VDD (stby) Parameter Power Supply Voltage Range of LED Drive Circuitry Minimum Standby Voltage Bits Retained in Display and Configuration Registers, Data Port Fully Functional Test Condition VDD V -- -- Guaranteed Limit 4.5 to 6.0 3.0 Unit V V
VIL VIH VHys VOL
Maximum Low-Level Input Voltage (Data In, Clock, Enable) Minimum High-Level Input Voltage (Data In, Clock, Enable) Minimum Hysteresis Voltage (Data In, Clock, Enable) Maximum Low-Level Output Voltage (Data Out) Iout = 20 A Iout = 1.3 mA
3.0 6.0 3.0 6.0 3.0 6.0 3.0 6.0 4.5 3.0 6.0 4.5 6.0 6.0 4.5 5.0 5.0 6.0 6.0 6.0 5.0 6.0
0.9 1.8 2.1 4.2 0.2 0.4 0.1 0.1 0.4 2.9 5.9 4.1 2.0 0.1 0.2 13 to 17.5 6 to 9 50 1 1 10 100
V V V V
VOH
Minimum High-Level Output Voltage (Data Out)
Iout = - 20 A Iout = - 800 A
V
Iin
Maximum Input Leakage Current (Data In, Clock, Enable)
Vin = VDD or VSS Vin = VDD or VSS, TJ = 25C only Vout = 1.0 V Rx = 2.0 k, Vout = 3.0 V, Dimmer Bit = High Rx = 2.0 k, Vout = 3.0 V, Dimmer Bit = Low
A
iOL iOH
Minimum Sinking Current (a, b, c, d, e, f, g, h) Peak Sourcing Current -- See Figure 9 for currents up to 35 mA (a, b, c, d, e, f, g, h)
mA mA
IOZ
Maximum Output Leakage Current (Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
Vout = VDD (FET Leakage) Vout = VDD (FET Leakage), TJ = 25C only Vout = VSS (Protection Diode Leakage)
A
Ron IDD, ISS
Maximum ON Resistance (Bank 1, Bank 2, Bank 3, Bank 4, Bank 5) Maximum Quiescent Supply Current
Iout = 0 to 200 mA Device in Low-Power Mode, Vin = VSS or VDD, Rx in Place, Outputs Open Same as Above, TJ = 25C
A
6.0 6.0
20 1.5 mA
Iss
Maximum RMS Operating Supply Current (The VSS leg does not contain the Rx current component. See Pin Descriptions.)
Device NOT in Low-Power Mode, Vin = VSS or VDD, Outputs Open
* See Thermal Considerations section.
MOTOROLA
MC14489 3
AC ELECTRICAL CHARACTERISTICS (TJ = - 40 to 130C*, CL = 50 pF, Input tr = tf = 10 ns)
Symbol fclk Parameter Serial Data Clock Frequency, Single Device or Cascaded Devices NOTE: Refer to Clock tw below (Figure 1) Maximum Propagation Delay, Clock to Data Out (Figures 1 and 5) Maximum Output Transistion Time, Data Out (Figures 1 and 5) Refresh Rate -- Bank 1 through Bank 5 (Figures 2 and 6) Maximum Input Capacitance -- Data In, Clock, Enable VDD V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 -- Guaranteed Limit dc to 3.0 dc to 4.0 dc to 4.0 140 80 80 70 50 50 NA 700 to 1900 700 to 1900 10 Unit MHz
tPLH, tPHL tTLH, tTHL fR
ns
ns
Hz
Cin
pF
* See Thermal Considerations section.
TIMING REQUIREMENTS (TJ = - 40 to 130C*, Input tr = tf = 10 ns unless otherwise indicated)
Symbol tsu, th Parameter Minimum Setup and Hold Times, Data In versus Clock (Figure 3) Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock (Figure 4) Minimum Active-Low Pulse Width, Enable (Figure 4) Minimum Inactive-High Pulse Width, Enable (Figure 4) Minimum Pulse Width, Clock (Figure 1) Maximum Input Rise and Fall Times -- Data In, Clock, Enable (Figure 1) VDD V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 Guaranteed Limit 50 40 40 150 100 100 4.5 3.4 3.4 300 150 150 167 125 125 1 1 1 Unit ns
tsu, th, trec tw(L)
ns
s
tw(H)
ns
tw
ns
tr, tf
ms
* See Thermal Considerations section. ** For a high-speed 8-Clock access, th for Enable is determined as follows: VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 - (7500/fclk) VDD = 4.5 to 6 V, fclk > 2.34 MHz: th = 3300 - (7500/fclk) where th is in ns and fclk is in MHz. NOTES: 1. This restriction does NOT apply for fclk rates less than those listed above. For "slow" fclk rates, use the th limits in the above table. 2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
MC14489 4
MOTOROLA
tf 90% CLOCK 50% 10% tw 1/fclk tPLH DATA OUT 90% 50% 10% tTLH
tr VDD VSS tw tPHL BANK OUTPUT tTHL 50% 1/fR
Figure 1.
Figure 2.
tw(L) VALID VDD DATA IN 50% VSS tsu CLOCK th 50% VSS VDD CLOCK tsu th ENABLE 50%
tw(H)
VDD VSS
trec VDD
50% FIRST CLOCK
LAST CLOCK
VSS
Figure 3.
Figure 4.
VDD TEST POINT TEST POINT 56 DEVICE UNDER TEST DEVICE UNDER TEST CL *
CL *
*Includes all probe and fixture capacitance.
Figure 5.
*Includes all probe and fixture capacitance.
Figure 6.
MOTOROLA
MC14489 5
PIN DESCRIPTIONS
DIGITAL INTERFACE Data In (Pin 12) Serial Data Input. The bit stream begins with the MSB and is shifted in on the low-to-high transition of Clock. When the device is not cascaded, the bit pattern is either 1 byte (8 bits) long to change the configuration register or 3 bytes (24 bits) long to update the display register. For two chips cascaded, the pattern is either 4 or 6 bytes, respectively. The display does not change during shifting (until Enable makes a low- to-high transition) which allows slow serial data rates, if desired. The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the two registers. Random access of either register is provided. That is, the registers may be accessed in any sequence. Data is retained in the registers over a supply range of 3 to 6 V. The format is shown in Figures 7 and 8. Information on the segment decoder is given in Table 1. Data In typically switches near 50% of VDD and has a Schmitt-triggered input buffer. These features combine to maximize noise immunity for use in harsh environments and bus applications. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail- to-rail. When interfacing to NMOS or TTL devices, either a level shifter (MC14504B, MC74HCT04A) or pullup resistor of 1 k to 10 k must be used. Parameters to be considered when sizing the resistor are the worst-case IOL of the driving device, maximum tolerable power consumption, and maximum data rate. Clock (Pin 11) Serial Data Clock Input. Low-to-high transitions on Clock shift bits available at Data In, while high-to-low transitions shift bits from Data Out. The chip's 24-1/2-stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. The Clock input does not need to be synchronous with the on-chip clock oscillator which drives the multiplexing circuit. Eight clock cycles are required to access the configuration register, while 24 are needed for the display register when the MC14489 is not cascaded. See Figures 7 and 10. As shown in Figure 11, two devices may be cascaded. In this case, 32 clock cycles access the configuration register and 48 access the display register, as depicted in Figure 8. Cascading of 3, 4, and 5 devices is shown in Figures 12, 13, and 14, respectively. Clock typically switches near 50% of V DD and has a Schmitt-triggered input buffer. Slow Clock rise and fall times are tolerated. See the last paragraph of Data In for more information. NOTE To guarantee proper operation of the power-on reset (POR) circuit, the Clock pin must NOT be floated or toggled during power-up. That is, the Clock pin must be stable until the V DD pin reaches at least 3 V. If control of the Clock pin during power-up is not practical, then the MC14489 must be reset via bit C0 in the C register. To accomplish this, C0 is reset low, then set high.
Enable (Pin 10) Active-Low Enable Input. This pin allows the MC14489 to be used on a serial bus, sharing Data In and Clock with other peripherals. When Enable is in an inactive high state, Data Out is forced to a known (low) state, shifting is inhibited, and the port is held in the initialized state. To transfer data to the device, Enable (which initially must be inactive high) is taken low, a serial transfer is made via Data In and Clock, and Enable is taken high. The low-to-high transition on Enable transfers data to either the configuration or display register, depending on the data stream length. Every rising edge on Enable initiates a blanking interval while data is loaded. Thus, continually loading the device with the same data may cause the LEDs on some banks to appear dimmer than others. NOTE Transitions on Enable must not be attempted while Clock is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs when Enable is high and Clock is low. This input is also Schmitt-triggered and switches near 50% of VDD, thereby minimizing the chance of loading erroneous data in the registers. See the last paragraph of Data In for more information. Data Out (Pin 18) Serial Data Output. Data is transferred out of the shift register through Data Out on the high-to-low transition of Clock. This output is a no connect, unless used in one of the manners discussed below. When cascading MC14489's, Data Out feeds Data In of the next device per Figures 11, 12, 13, and 14. Data Out could be fed back to an MCU/MPU to perform a wrap-around test of serial data. This could be part of a system check conducted at power-up to test the integrity of the system's processor, pc board traces, solder joints, etc. The pin could be monitored at an in-line Q.A. test during board manufacturing. Finally, Data Out facilitates troubleshooting a system. DISPLAY INTERFACE Rx (Pin 8) External Current-Setting Resistor. A resistor tied between this pin and ground (VSS) determines the peak segment drive current delivered at pins a through h. Pin 8's resistor ties into a current mirror with an approximate current gain of 10 when bit D23 = high (brighten). With D23 = low, the peak current is reduced about 50%. Values for Rx range from 700 to infinity. When Rx = (open circuit), the display is extinguished. For proper current control, resistors having 1% tolerance should be used. See Figure 9. CAUTION Small Rx values may cause the chip to overheat if precautions are not observed. See Thermal Considerations.
MC14489 6
MOTOROLA
a through h (Pins 1, 2, 4 - 7, 19, 20) Anode-Driver Current Sources. These outputs are closely-matched current sources which directly tie to the anodes of external discrete LEDs (lamps) or display segment LEDs. Each output is capable of sourcing up to 35 mA. When used with lamps, outputs a, b, c, and d are used to independently control up to 20 lamps. Output h is used to control up to 5 lamps dependently. (See Figure 17.) For lamps, the No Decode mode is selected via the configuration register, forcing e, f, and g inactive (low). When used with segmented displays, outputs a through g drive segments a through g, respectively. Output h is used to drive the decimals. If unused, h must be left open. Refer to Figure 10. Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17) Diode-Bank FET Switches. These outputs are low-resistance switches to ground (VSS) capable of handling currents of up to 320 mA each. These pins directly tie to the common cathodes of segmented displays or the cathodes of lamps (wired with cathodes common). The display is refreshed at a nominal 1 kHz rate to achieve optimum brightness from the LEDs. A 20% duty cycle is utilized.
Special design techniques are used on-chip to accommodate the high currents with low EMI (electromagnetic interference) and minimal spiking on the power lines. POWER SUPPLY VSS (Pin 14) Most-negative supply potential. This pin is usually ground. Resistor Rx is externally tied to ground (VSS). Therefore, the chip's VSS pin does not contain the Rx current component. VDD (Pin 13) Most-positive supply potential. To guarantee data integrity in the registers and to ensure the serial interface is functional, this voltage may range from 3 to 6 volts with respect to VSS. For example, within this voltage range, the chip could be placed in and out of the low- power mode. To adequately drive the LEDs, this voltage must be 4.5 to 6 volts with respect to VSS. The V DD pin contains the Rx current component plus the chip's current drain. In the low-power mode, the current mirror and clock oscillator are turned off, thus significantly reducing the VDD current, IDD.
MOTOROLA
MC14489 7
CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC
LSB C5 C4 C3 C2 C1 C0 L = LOW POWER MODE (BLANKS THE DISPLAY), FORCED LOW (L) BY POWER ON RESET H = NORMAL MODE CONTROLS BANK 1: L = HEX DECODE, H = DEPENDS ON C6 NOTE: The low-power (standby) mode places the device CONTROLS BANK 2: L = HEX DECODE, H = DEPENDS ON C6 in a static state, thus eliminating EMI and mux switching noise. Therefore, during precision analog measurements, CONTROLS BANK 3: L = HEX DECODE, H = DEPENDS ON C6 the low-power mode could be invoked by a system's MCU. CONTROLS BANK 4: L = HEX DECODE, H = DEPENDS ON C7 Also, the low-power mode blanks the display, and could CONTROLS BANK 5: L = HEX DECODE, H = DEPENDS ON C7 be used to flash the LEDs on and off. L = NO DECODE, H = SPECIAL DECODE (REFER TO C1, C2, AND C3) L = NO DECODE, H = SPECIAL DECODE (REFER TO C4 AND C5) SEE TABLE 1
Figure 7. Timing Diagrams for Non-Cascaded Devices
CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC
LSB D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BANK 5 NIBBLE = ALL h OUTPUTS INACTIVE BANK 4 NIBBLE BANK 3 NIBBLE BANK 2 NIBBLE SEE TABLE 1 BANK 1 NIBBLE = ACTIVATE h IN BANK 1 = ACTIVATE h IN BANK 2 = ACTIVATE h IN BANK 3 = ACTIVATE h IN BANK 4 = ACTIVATE h IN BANK 5 = ACTIVATE h IN BOTH BANKS 1 AND 2 = ACTIVATE h IN ALL BANKS L L L L H H H H L L H H L L H H L H L H L H L H THE LSBs OF EACH BANK NIBBLE ARE D0, D4, D8, D12, AND D16.
MC14489 8
2 3 4 5 6 7 8
ENABLE
CLOCK
1
MSB
DATA IN
C7
C6
(a) Configuration Register Format (1 Byte)
ENABLE
CLCOK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSB
DATA IN
D23
D22
L = DIM LEDs, H = BRIGHTEN LEDs
(b) Display Register Format (3 Bytes)
NOTE: L = Low Voltage Level (Logic 0), H = High Voltage Level (Logic 1)
MOTOROLA
Table 1. Triple-Mode Segment Decoder Function Table
Lamp Conditions No Decode (Invoked via Bits C1 to C7)
Bank Nibble Value
7-Segment Display Characters Hex Decode (Invoked via Bits C1 to C5) Special Decode (Invoked via Bits C1 to C7)
Hexadecimal $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
Binary MSB LSB L L L L L L L L H H H H H H H H LL LL LH LH HL HL HH HH LL LL LH LH HL HL HH HH L H L H L H L H L H L H L H L H
d
c
b
a
on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on
NOTES: 1. In the No Decode mode, outputs e, f, and g are unused and are all forced inactive (low). Output h decoding is unaffected, i.e., unchanged from the other modes. The No Decode mode is used for three purposes: a. Individually controlling lamps. b. Controlling a half digit with sign. c. Controlling annunciators - examples: AM, PM, UHF, kV, mm Hg. 2. Can be used as capital S. 3. Can be used as capital B. 4. Can be used as small g.
MOTOROLA
MC14489 9
C7
C6
C5
C4
C3
C2
C1
C0
1ST BYTE SHIFTED IN CONFIGURATION REGISTER OF DEVICE 2 IN FIGURE 11
2ND BYTE
3RD BYTE
4TH BYTE
DON'T CARE
DON'T CARE
CONFIGURATION REGISTER OF DEVICE 1 IN FIGURE 11
(a) Configuration Registers
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1ST BYTE SHIFTED IN h BITS AND DIMMER BIT BANK 5 NIBBLE
2ND BYTE
3RD BYTE
4TH BYTE
5TH BYTE
6TH BYTE
BANK 4 NIBBLE
BANK 3 NIBBLE
BANK 2 NIBBLE
h BITS BANK BANK BANK AND 1 4 5 NIBBLE DIMMER NIBBLE NIBBLE BIT
BANK 3 NIBBLE
BANK 2 NIBBLE
BANK 1 NIBBLE
DISPLAY REGISTER OF DEVICE 2 IN FIGURE 11
DISPLAY REGISTER OF DEVICE 1 IN FIGURE 11
(b) Display Registers
NOTE: ENABLE (which initially must be inactive high) is kept active-low during the entire 4-byte configuration transfer or 6-byte display transfer. When ENABLE is brought back high, either a 4- or 6-byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer.
Figure 8. Bit Stream Formats for Two Devices Cascaded
35 i OH, PEAK DRIVE CURRENT (mA) 30 25 20 15 10 5 400
5 V SUPPLY BIT D23 = HIGH (BRIGHTEN LEDs) WITH D23 = LOW, iOH IS CUT BY 50%.
800
1.2 k
1.6 k
2.0 k
2.4 k 2.8 k
3.2 k
3.6 k
4.0 k
Rx, EXTERNAL RESISTOR () NOTE: Drive current tolerance is approximately 15%.
Figure 9. a through h Nominal Current per Output versus Rx
MC14489 10
MOTOROLA
APPLICATIONS INFORMATION
+5V MC14489 VDD VSS a b c d e f g h * #5 BANK 5 CMOS MCU/MPU DATA IN CLOCK ENABLE BANK 4 BANK 3 BANK 2 BANK 1 #4

8 8 8 8 8 8
OPTIONAL +5V Rx
DATA OUT Rx
a f e g d #1 b c
#3
#2
Figure 10. Non-Cascaded Application Example: 5 Character Common Cathode LED Display with Two Intensities as Controlled via Serial Port
a TO h
BANK 1 TO BANK 5
a TO h
BANK 1 TO BANK 5
MC14489 #1 DATA IN DATA OUT DATA IN
MC14489 #2 DATA OUT
CLOCK
ENABLE
CLOCK
ENABLE
CMOS MCU/MPU OPTIONAL
Figure 11. Cascading Two Devices
MOTOROLA
MC14489 11
MC14489 12
a TO h MC14489 #1 DATA IN CLOCK ENABLE CLOCK CLOCK ENABLE ENABLE DATA OUT DATA IN DATA OUT DATA IN DATA OUT MC14489 #2 MC14489 #3 BANK 1 TO BANK 5 a TO h BANK 1 TO BANK 5 a TO h BANK 1 TO BANK 5 OPTIONAL
CMOS MCU/MPU
(a) Cascading Three Devices
C7 C6 C5 C4 C3 C2 C1 C0
1ST BYTE SHIFTED IN 2ND BYTE DON'T CARE DON'T CARE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE CONFIGURATION REGISTER OF DEVICE #3 CONFIGURATION REGISTER OF DEVICE #2 DON'T CARE
7TH BYTE
8TH (LAST) BYTE DON'T CARE CONFIGURATION REGISTER OF DEVICE #1
DON'T CARE
(b) Configuration Registers
D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22
D21 D20 D19
MOTOROLA
NOTE: When the leading "don't care" bytes are included, ENABLE (which initially must be inactive high) is kept active-low during the entire 8-byte configuration transfer or 10-byte display transfer. When ENABLE is brought back high, either an 8- or 10-byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the one "don't care" byte can be eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t w (H) spec, (4) transfer last 3 bytes, and (5) take ENABLE inactive high.
Figure 12. Bit Stream Formats for Three Devices Cascaded
2ND BYTE h BITS AND DIMMER BIT BANK 5 NIBBLE DISPLAY REGISTER OF DEVICE #3 BANK 4 NIBBLE BANK 3 NIBBLE BANK 2 NIBBLE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE BANK 4 NIBBLE 7TH BYTE h BITS BANK BANK AND 1 5 DIMMER NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #2
1ST BYTE SHIFTED IN
8TH BYTE
9TH BYTE
10TH (LAST) BYTE BANK BANK BANK h BITS BANK BANK BANK BANK BANK AND 3 2 1 5 4 3 2 1 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #1
DON'T CARE (OPTIONAL, SEE NOTE)
(c) Display Registers
MOTOROLA
BANK 1 TO BANK 5 a TO h a TO h MC14489 #3 DATA OUT DATA IN CLOCK ENABLE CLOCK DATA OUT DATA IN MC14489 #4 ENABLE DATA OUT MC14489 #2 DATA OUT CLOCK ENABLE DATA IN BANK 1 TO BANK 5 BANK 1 TO BANK 5 a TO h BANK 1 TO BANK 5 MC14489 #1 ENABLE OPTIONAL
a TO h
DATA IN
CLOCK
CMOS MCU/MPU
(a) Cascading Four Devices
C5 C4 C3 C2 C1 C0
C7
C6
1ST BYTE SHIFTED IN 3RD BYTE 5TH BYTE 6TH BYTE 8TH BYTE 4TH BYTE 7TH BYTE CONFIGURATION REGISTER OF DON'T CARE DEVICE #4 DON'T CARE DON'T CARE DON'T CARE CONFIGURATION REGISTER OF DEVICE #3
2ND BYTE
9TH BYTE
10TH BYTE
11TH BYTE
12TH (LAST) BYTE DON'T CARE CONFIGURATION REGISTER OF DEVICE #1
DON'T CARE DON'T CARE
CONFIGURATION REGISTER OF DON'T CARE DEVICE #2
(b) Configuration Registers
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
MC14489 13
NOTE: When the leading "don't care" bytes are included, ENABLE (which initially must be inactive high) is kept active-low during the entire 12-byte configuration transfer or 14-byte display transfer. When ENABLE is brought back high, either a 12- or 14-byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the two "don't care" bytes can be eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t w (H) spec, (4) transfer last 6 bytes, and (5) take ENABLE inactive high.
Figure 13. Bit Stream Formats for Four Devices Cascaded
3RD BYTE h BITS BANK BANK BANK BANK AND 5 4 3 2 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #4 4TH BYTE 5TH BYTE 6TH BYTE 7TH BYTE 8TH BYTE BANK h BITS BANK BANK BANK BANK BANK 1 5 4 3 1 AND 2 NIBBLE DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #3
1ST BYTE SHIFTED IN
2ND BYTE
12TH BYTE
13TH BYTE
14th (LAST) BYTE h BITS BANK BANK BANK BANK BANK AND 4 3 2 1 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #1
DON'T CARE (OPTIONAL, SEE NOTE)
DON'T CARE (OPTIONAL, SEE NOTE)
(c) Display Registers
MC14489 14
BANK 1 TO BANK 5 a TO h a TO h MC14489 #3 DATA OUT DATA IN CLOCK ENABLE CLOCK DATA OUT DATA IN MC14489 #5 ENABLE DATA OUT MC14489 #2 DATA OUT CLOCK ENABLE DATA IN BANK 1 TO BANK 5 a TO h MC14489 #1 ENABLE BANK 1 TO BANK 5 BANK 1 TO BANK 5 OPTIONAL
a TO h
DATA IN
CLOCK
CMOS MCU/MPU
(a) Cascading Five Devices
C5 C4 C3 C2 C1 C0
C7
C6
1ST BYTE SHIFTED IN 3RD BYTE 5TH BYTE 6TH BYTE 8TH BYTE 4TH BYTE 7TH BYTE
2ND BYTE
9TH BYTE
10TH BYTE
11TH BYTE
12TH BYTE
13TH (LAST) BYTE
CONFIGURATION CONFIGURATION CONFIGURATION CONFIGURATION CONFIGURATION REGISTER OF DON'T CARE DON'T CARE REGISTER OF DON'T CARE DON'T CARE REGISTER OF DON'T CARE DON'T CARE REGISTER OF DON'T CARE DON'T CARE REGISTER OF DEVICE #3 DEVICE #1 DEVICE #2 DEVICE #5 DEVICE #4
(b) Configuration Registers
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
Figure 14. Bit Stream Formats for Five Devices Cascaded
1ST BYTE SHIFTED IN 2ND BYTE 3RD BYTE h BITS BANK BANK BANK BANK AND 4 3 2 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #5 4TH BYTE 5TH BYTE 6TH BYTE h BITS BANK BANK BANK BANK BANK BANK AND 4 3 2 1 5 1 DIMMER NIBBLE BIT NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE DISPLAY REGISTER OF DEVICE #4
13TH BYTE
14TH BYTE
15TH (LAST) BYTE h BITS BANK BANK BANK BANK BANK AND 4 3 2 1 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE #1
(c) Display Registers
MOTOROLA
NOTE: ENABLE (which initially must be inactive high) is kept active-low during the entire 13-byte configuration transfer or 15-byte display transfer. When ENABLE is brought back high, either a 13- or 15-byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer.
LED DISPLAY
+5V
8
5
+5V VDD
CMOS MCU/MPU
R1 MC14489 Rx R2 VSS
NOTE: R1 limits the maximum current to avoid damaging the display and/or the MC14489 due to overheating. See the Thermal Considerations section. An 1/8 watt resistor may be used for R1. R2 is a 1 k or 5 k potentiometer ( 1/8 watt). R2 may be a light-sensitive resistor.
Figure 15. Common-Cathode LED Display with Dial-Adjusted Brightness
UNIVERSAL OVERFLOW ("1" OR "HALF-DIGIT")
5-DIGIT DISPLAY
USE TO DRIVE LAMP OR MINUS SIGN
7
h
1
23 4 5 BANK OUTPUTS
a TO g
MC14489
3 INPUT LINES NOTE: A Universal Overflow pins out all anodes and cathodes.
Figure 16. Driving 5 1/2 Digits
MOTOROLA
MC14489 15
a b MC14489 c d e f g h NC NC NC
THESE LAMPS INDEPENDENTLY CONTROLLED WITH BITS D0 TO D19
BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 THESE LAMPS DEPENDENTLY CONTROLLED WITH BITS D20, D21, AND D22*
3
CMOS MCU/MPU
* If required, this group of lamps can be independently controlled. To accomplish independent control, only connect lamps to BANK 1 and BANK 2 for output h (two lamps). Then, use bits D20, D21, and D22 for control of these two lamps.
Figure 17. 25-Lamp Application
MC14489 16
MOTOROLA
4
*
4 a TO d
4 e TO h
4 BANK 1 TO BANK 4 BANK 5 MC14489
3
CMOS MCU/MPU
Figure 18. 4-Digit Display Plus Decimals with Four Annunciators or 4-1/2-Digit Display Plus Sign
MUXED 5-DIGIT MONOLITHIC DISPLAY (CLUSTER) HEWLETT-PACKARD 5082-7415 OR EQUIVALENT
14
12
3
6
2
10
8
5
1
13
4
9
7
7
6
5
4
2
1
20
19
17
16
15
13
9
8
MC14489
3 INPUT LINES
Figure 19. Compact Display System with Three Components
MOTOROLA
MC14489 17
THERMAL CONSIDERATIONS
The MC14489 is designed to operate with a chip-junction temperature (TJ) ranging from - 40 to 130C, as indicated in the electrical characteristics tables. The ambient operating temperature range (TA) is dependent on RJA, the internal chip current, how many anode drivers are used, the number of bank drivers used, the drive current, and how the package is cooled. The maximum ratings table gives the thermal resistance, junction-to-ambient, of the MC14489 mounted on a pc board using natural convection to be 90C per watt for the plastic DIP. The SOG thermal resistance is 100C per watt. The following general equation (1) is used to determine the power dissipated by the MC14489. PT = PD + PI where PT = Total power dissipation of the MC14489 PD = Power dissipated in the driver circuitry (mW) PI = Power dissipated by the internal chip circuitry (mW) The equations for the two terms of the general equation are: PD = (iOH) (N)(VDD - VLED)(B/5) PI = (1.5 mA)(VDD) + IRx(VDD - IRxRx) (2) (3) (1) PI = (1.5)(5.25) + 2[5.25 - 2(2)] = 10 mW Therefore, PT = 552 + 10 = 562 mW and Tchip = RJAPT = (90C/W)(0.562) = 51C Finally, the maximum allowable TA = TJmax - Tchip = 130 - 51 = 79C That is, if TA = 79C, the maximum junction temperature is 130C. The chip's average temperature for this example is lower than 130C because all segments are usually not illuminated simultaneously for an indefinite period. Worst-Case Analysis Example 2: 16 lamps (4 banks and 4 anode drivers) SOG without heat sink on PC board iOH = 30 mA max VLED = 1.8 V min VDD = 5.5 max PD = (30)(4)(5.5 - 1.8)(4/5) = 355 mW PI = (1.5)(5.5) + 3[5.5 - 3(1.0)] = 16 mW Therefore, PT = 355 + 16 = 371 mW and Tchip = RJAPT = (100C/W)(0.371) = 37C Finally, the maximum allowable TA = TJmax - Tchip = 130 - 37 = 93C To extend the allowable ambient temperature range or to reduce TJ, which extends chip life, a heat sink such as shown in Figure 20 can be used in high-current applications. Alternatively, heat-spreader techniques can be used on the PC board, such as running a wide trace under the MC14489 and using thermal paste. Wide, radial traces from the MC14489 leads also act as heat spreaders. Ref. (2) Ref. (3) Ref. (1) Ref. (3) Ref. (1)
where iOH = Peak anode driver current (mA) IRx = iOH /10, with iOH = the peak anode driver current (mA) when the dimmer bit is high N = Number of anode drivers used B = Number of bank drivers used Rx = External resistor value (k) VDD = Maximum supply voltage, referenced to VSS (volts) VLED = Minimum anticipated voltage drop across the LED 1.5 mA = Operating supply current of the MC14489 The following two examples show how to calculate the maximum allowable ambient temperature. Worst-Case Analysis Example 1: 5-digit display with decimals (5 banks and 8 anode drivers) DIP without heat sink on PC board iOH = 20 mA max VLED = 1.8 V min VDD = 5.25 max PD = (20)(8)(5.25 - 1.8)(5/5) = 552 mW Ref. (2)
AAVID #5804 or equivalent (Tel. 603/524-4443, FAX 603/528-1478) Motorola cannot recommend one supplier over another and in no way suggests that this is the only heat sink supplier.
Figure 20. Heat Sink
MC14489 18
MOTOROLA
Table 2. LED Lamp and Common-Cathode Display Manufacturers
Supplier QT Optoelectronics Hewlett-Packard (HP), Components Group Industrial Electronic Engineers (IEE), Component Products Div. Purdy Electronics Corp., AND Product Line Contact Information Phone: (800) 533-6786 FAX: (214) 447-0784 Contact your local HP Components Sales Office Phone: (818) 787-0311 FAX: (818) 901-9046 Phone: (408) 523-8210 FAX: (408) 733-1287
NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of LED suppliers.
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP CASE 738-03 -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 1.01 0.51
B
1 10
C
L
-TSEATING PLANE
K M E G F D 20 PL 0.25 (0.010)
M
N J 20 PL 0.25 (0.010) TA
M
M
TB
M
MOTOROLA
MC14489 19
DW SUFFIX SOG PACKAGE CASE 751D-04 -A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R C -T-
18X SEATING PLANE X 45 _
G
K
M
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC14489 20
*MC14489/D*
MC14489/D MOTOROLA

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